1. Technical Field of the Invention
This invention relates generally to the manufacture of micro-electrical circuits, and, more particularly, to the formation of uniform-thickness metallization bumps on terminal areas of electrical circuits on a substantially planar substrate, particularly near the edge thereof.
2. Background Information
The present invention has utility in the plating of metallization bumps on predetermined terminal areas of silicon wafers prior to scribing such wafers into a plurality of individual die.
FIG. 1 shows a silicon wafer 3 upon which a plurality of individual electrical circuit elements 6 are formed. The electrical characteristics of individual circuit elements 6 may be imparted to them by employing any suitable process(es) therefor. The specifics of the electrical circuit of the circuit elements 6 lies outside of the scope of the present invention.
FIG. 2 shows a view similar to that shown in FIG. 1, wherein the wafer 3 has been separated into pieces 7 including at least one die 8 using conventional wafer scribing or sawing techniques.
FIGS. 3A show steps in the formation of a terminal region 19 on a surface of an individual die 8, prior to wafer scribing or sawing, and the plating of a metallization bump onto such terminal region 19. In the manufacture of a particular electrical product from die 8, such as the double-slug diode shown in FIG. 4, it is frequently necessary to deposit a metallized bump in a predetermined area of a surface of such die.
Referring to FIG. 3A, a representative individual die 8 of wafer 3 is shown overlaid with a layer of oxide 38, and a hole or window 18 has been etched through the oxide 38 down to a terminal area (not shown) of the underlying substrate 28.
In FIG. 3B, the window 18 of FIG. 3A has been filled with top metal 19. In a preferred embodiment of the invention, the top metal 19 actually comprises three layers: first a layer of titanium, next a layer of nickel, and finally a layer of silver. Again, the composition of the layers and thickness thereof are not specific to the present invention.
In FIG. 3C, a metallization bump, comprising a layer of silver 14 and a layer of tin 15, has been electro-deposited over the top metal terminal region 19.
FIG. 4 shows a double-slug diode manufactured according to the method and apparatus disclosed by the present invention. The diode of FIG. 4 is shown for illustrative purposes only, and it should be understood by all practitioners in the art that the present invention has broad utility in many metallization bump processing applications and is not intended to be limited to implementations such as that shown in FIGS. 3 and 4.
Still with reference to FIG. 4, the die 8 has been separated from its counterparts on wafer 3 and mounted between copper "slugs" or terminals 16 and 17 to which electrical leads 41 and 42, respectively, have been affixed. The entire assembly is enclosed in glass 9.
FIG. 5 shows a prior art plating apparatus for plating metallization bumps onto predetermined terminal areas of a silicon wafer, such as terminal area 19 of die 8. Referred to as a rack plating apparatus, it comprises a tank 1 of electroplating solution into which an anode 5 and a cathode 4 are shown partially submersed. It will be understood that anode 5 and cathode 4 are shown partially submersed for ease in understanding and that during operation they are substantially submersed.
Anode 5 has a potential having a positive polarity coupled thereto, while cathode 4 has a potential having a negative polarity coupled thereto.
Affixed to cathode 4 is a substantially planar, conductive wafer 3 comprising a plurality of individual electrical elements (not shown), each with a terminal area such as terminal area 19 shown in FIG. 3B. It will be understood by those skilled in the art that substrate 3 may itself serve as the cathode 4, or substrate 3 may be suitably affixed to a wafer carrier, which serves as the cathode 4.
FIG. 6 is a graph illustrating the variation of bump height across a silicon wafer electroplated with the prior art plating apparatus shown in FIG. 5. The bump height in microns measured on selected die is provided along the Y-axis, and the die position across a given wafer diameter is provided along the X-axis. It will be observed that the X-axis of FIG. 6 is non-linerar, in that emphasis is given to die numbers closest to the wafer edge, for example die numbers 1-5 at the left edge and die number 184-188 at the right edge.
It is seen that when metallized bumps are plated with the apparatus shown in FIG. 6 there is substantial variation in bump height across the wafer diameter. The bumps are highest at or near the wafer edge. For example, the bump height 11 of die #1 is 70 microns, and that of die #188 is approximately 58 microns, whereas that of die #120 is approximately 41 microns.
According to the graph of FIG. 6, the bump height variation across a typical 9.65 centimeter diameter wafer is almost 30 microns, ranging from a minimum of 41 microns at die #120 to a maximum of 70 microns at die #1. This greatly exceeds a desired production specification width of 20 microns.
The increased electroplating intensity near the wafer edge is commonly referred to as "edge effect".
Therefore, there is a substantial need to provide an electroplating method and apparatus which overcomes the "edge effect" problem known in prior electroplating systems.
Various electroplating systems are known which have attempted to overcome the "edge effect". One such system is referred to as a cathode-mask system, in which the high-growth area of the substrate is masked. However, this system suffers from the need to achieve critcal positioning of the mask relative to the high-growth area of the substrate. Both the alignment of the mask and the mask-to-wafer spacing are critical and difficult to control.